The invention relates to data management and analysis systems and methods, and more particularly, to real-time management systems and methods for manufacturing management and yield rate analysis integration.
Lot yield is important in semiconductor manufacturing, representing for not only manufacturing technology but also costs. Yield rate affects profits, such that increased yield poses a major concern in semiconductor manufacturing.
Complex industrial processes, such as those used in the manufacture of semiconductor integrated circuit devices, typically require tens to hundreds of tightly controlled individual steps and parameters to complete. Yield rate susceptibility is affected by electrical performance and performance of semiconductor equipment.
Defect testing checks and measures yield rate during the manufacturing process. Testing occurs after a product completes an individual step, with electrical testing measuring yield rate, after which the semiconductor product proceeds to the next step.
Inline defect testing scans for contamination or defects. Traditionally, defect testing analyzes yield rate from a single semiconductor tool or process, or like tools or processes, and cannot quickly identify problem sources in semiconductor equipment over multiple steps or unlike processes.
Additionally, defects in wafer products impact manufacturing cost and competition due to development of more accurately designed circuits relating to semiconductor manufacturing. Yield rate improvement and enhancement reduces manufacturing cost, and increases profit and industry competitiveness. Therefore, process control and engineer data analysis (EDA) technologies are implemented in the above purposes. With yield rate loss of wafer lots, detecting and improvement of possible causes if important, utilizing analysis of industrial data and determination based on experience and knowledge.
Generally, when analysis relating to yield rate loss of wafer lots is implemented, manufacturing data comprising process parameters, tool parameters, wafer defect data, wafer acceptance test (WAT) data, circuit probing (CP) data, and yield rate data is considered. Additionally, only one engineer is responsible to one type data that long time discussion between all engineers is required. Further, related manufacturing data from the beginning of a process to the final test affects to yield rates.
Current yield rate improvement methods attribute probable causes to yield rates according to one type of data, such as “Regression Tree Analysis (RTA)” disclosed in “Yield rate improvement using data mining system semiconductor manufacturing,” IEEE International Symposium on. Conference Proceedings, 391–394 (1999) by Mieno et al. The RTA method is implemented in oxide process to prevent wafer yield rate loss, revealing variation parameters from a great number of process parameters to improve process drawbacks for yield rate promotion. With respect to defect analysis, Ken discloses signature of defect clustered concepts in “Using full wafer defect maps as process signatures to monitor and control yield rate,” IEEE/SEMI Semiconductor Manufacturing Science Symposium, 129–135 (1991), using statistical process control (SPC) methods to detect clustered defects. Defects are not randomly distributed but clustered, whereby holography extraction can be utilized for determination, requiring extensive storage space.
As described, current yield rate loss analysis methods are performed on only one type data, although manufacturing data has relationships therebetween and yield rate loss issues can only be focused according thereto. Thus, an improved data analysis for yield rate improvement is desirable.